Technical Field
The present disclosure relates to the field of integrated circuit dies and, more particularly, to the application of bias voltages to the body regions of transistors in an integrated circuit die.
Description of the Related Art
Many types of electronic devices include integrated circuit dies. The integrated circuit dies can include millions or even billions of transistors. As the number of transistors increases, so too can the power consumed by the integrated circuit die. Handheld or other portable electronic devices typically are powered by one or more batteries. The higher the rate of power consumption, the more quickly the batteries become depleted. Thus, many schemes have been devised to reduce the rate of power consumption.
One way to reduce power consumption in an electronic device is to lower the operating voltage. In devices that include an SRAM array, the minimum operating voltage of the SRAM array can become a limiting factor in reducing the operating voltage. This is because at low voltages, the temperature of the semiconductor substrate can affect the reliability of both read and write operations of the SRAM. In particular, SRAM bit cells can have conflicting requirements for read and write operations with regard to temperature and operating voltage.
Each SRAM bit cell typically includes both NMOS and PMOS transistors. The threshold voltage of both NMOS and PMOS transistors increases with decreasing temperature. Higher temperatures can lead to an increase in failures during read operations, i.e., destructive reads, or flipping of stored data during read operations from an SRAM bit cell. Conversely, lower temperatures can lead to an increase in failures during write operations. This effect of temperature is generally predominant at low voltage operation of the SRAM bit cell.